MAJORITY-ENHANCED TREE STRUCTURE MULTIPLIER

Abstract

Multiplication is a fundamental operation in digital circuits, and designing efficient multipliers is crucial for achieving high-performance computing systems. The Wallace Tree Multiplier is a well-known architecture that enhances speed and reduces area by utilizing partial product reduction techniques. In this Project, we propose a novel approach to further optimize the Wallace Tree Multiplier by replacing conventional adders with Majority Gate-based Adders.
Majority gates, known for their simplicity and compactness, operate by outputting the majority value among their inputs. We leverage the unique characteristics of Majority Gate-based Adders to improve the performance of the multiplier in terms of speed and area. The proposed design exploits the inherent parallelism of majority gate operations, allowing for faster accumulation of partial products in the Wallace Tree structure