IMPLEMENTATION OF EFFICIENT AND LOW POWER TEST PATTERN GENERATORS

Abstract

We are aware that during testing when the device’s normal functioning mode is off, the dissipation of power is approximately 200% more than that of normal functioning mode. In this project 32-bit test pattern generator has been proposed for testing the VLSI design. This 32-bit test pattern generator is implemented with efficient LFSR and with extra combinational circuitry which achieved Low power consumption. The switching activity between the tests vector are reduced, this results in low power consumption .