DESIGN AND ANALYSIS OF 8-BIT MULTIPLIER FOR LOW POWER VLSI APPLICATIONS

Abstract

The multiplier stands as a fundamental component within the multiply and accumulate (MAC) unit, particularly prevalent in digital signal processing (DSP) applications. Traditionally, multiplication involves repeated addition, leading to extensive use of full adders (FAs) in the process. The energy efficiency of the multiplier is gauged by power delay per bit operation. Consequently, the efficiency of the multiplier hinges significantly on the role played by the full adder. In this project conducts a comprehensive study, design, implementation and simulation of an 8-bit additive multiply module (AMM), employing diverse full adder circuit architectures. The designed AMM is then compared with traditional Wallace/Dadda tree multipliers across various design metrics. For the purpose of comparison, all multipliers are described using RTL codes, and the designs are simulated and verified using EDA tools