DESIGN AND ANALYSIS OF MAJORITY LOGIC BASED APPROXIMATE ADDERS AND MULTIPLIERS

Abstract

Approximate computing (AC) introduces advantages by relaxing the demand for full accuracy, consequently lowering power consumption and area requirements. The Majority Logic (ML) gate serves as a fundamental logic block in numerous emerging nanotechnologies. This Project proposes ML-based arithmetic circuits, specifically multibit adders and multipliers. These adders are meticulously crafted to prevent the propagation of inaccurate carry-out signals to higher-order computing components, thereby enhancing overall accuracy. For the proposed multiplier, a distinctive Partial Product Reduction (PPR) circuitry is implemented, based on the parallel approximate 6:3 compressor. Extensive analyses of logic implementation costs, error metrics, and layouts are conducted using Majority Logic to assess the efficiency of the adder designs. Experimental results showcase a substantial improvement compared to previous ML-based designs.