EFFICIENT IMPLEMENTATION OF 2,4,8 BIT MULTIPLIERS WITH “URDHAVA TRIYAKBHYAM” VEDIC ALGORITHM

Abstract

This Project presents a VLSI implementation of a Vedic multiplier utilizing the Urdhva– Tiryakbhyam Sutra, a traditional Indian mathematical technique, within a Verilog environment. The proposed design leverages the sutra's unique mathematical principles to achieve efficient and high-speed multiplication.
The Verilog implementation ensures a seamless integration into digital circuits. The utilization of VLSI technology enhances the overall performance, making the multiplier suitable for modern computational applications. We are designing 2x2,4x4 and 8x8 multipliers. The results demonstrate the effectiveness of the Vedic multiplier in terms of speed and resource utilization, establishing its relevance in modern digital systems.