DESIGN AND IMPLEMENTATION OF DIRECT AND POST TRUNCATED ADDER TREE

Abstract

In this project, a novel scheme is presented to obtain fixed width AT design using truncated input. Conventionally, fixed-width adder-tree (AT) design is obtained from the full-width AT design by employing direct or post-truncation. In direct-truncation, one lower order bit of each adder output of full-width AT is post-truncated, and in case of post-truncation, “p” lower order- bits of final-stage adder output are truncated. The proposed fixed-width AT design for input- vector sizes 8 offers (37%; 23%; 22%) and (51%; 30%; 27%) area saving for word-length sizes (8; 12; 16), respectively, and calculates the output almost with the same accuracy as the post- truncated fixed-width AT which has the highest accuracy among the existing fixed-width AT.