HIGH SPEED AREA EFFICIENT VLSI ARCHITECTURE OF THREE OPERAND BINARY ADDER

Abstract

The three-operand binary adder serves as a fundamental unit for modular arithmetic in cryptography and pseudorandom bit generator algorithms. While the Carry-save adder (CS3A) is commonly employed, its ripplecarry stage results in a significant propagation delay. Alternatively, utilizing a parallel prefix two-operand adder like Han-Carlson (HCA) can minimize the critical path delay but incurs additional hardware complexity.
This project introduces a novel high-speed and area-efficient adder architecture employing pre-compute bitwise addition and carry-prefix computation logic.
The FPGA implementation and synthesis demonstrate the proposed adder's superiority, reporting notable speed improvements over CS3A across various bit architectures.
Additionally, the new adder exhibits reduced area, lower power consumption, and smaller delay compared to the HC3A adder, achieving superior ADP and PDP metrics in three-operand addition techniques.