DESIGN OF SRAM BASED FAST ERROR-RESILIENT TERNARY CONTENT ADDRESSABLE MEMORY

Abstract

Content Addressable Memory (CAM) plays a critical role in high-speed search operations within networking and communication devices. SRAMs implementing TCAM contents constitute a major part of a TCAM design on FPGAs, which are vulnerable to soft errors. The protection of SRAM-based TCAMs against soft errors is challenging without compromising critical path delay and maintaining a high search performance. SRAM-based TCAM emulations are susceptible to errors due to various factors such as process variations, aging effects, and radiation-induced soft errors. In this Project, we present a comprehensive study on the error detection and correction techniques specifically tailored for SRAM emulated TCAMs. We introduce a novel error detection mechanism based on parity checking, capable of identifying and correcting single-bit errors and detecting the presence of multi-bit errors within the stored data.